Author：Wall Street CN

Supply-side constraints on AI computing infrastructure are spreading from chip manufacturing to optical components and advanced packaging materials. Broadcom executives have for the first time identified three major bottlenecks in the AI supply chain, revealing that the true obstacles to this computing power arms race are far deeper than the market generally perceives, and are unlikely to be resolved in the short term.

At a media briefing held in Taipei on March 24, Natarajan Ramachandran, Director of Product Marketing for Physical Layers at Broadcom, pointed out that the AI-related supply chain is currently facing three core bottlenecks:Laser production capacity, wafers (specifically TSMC's advanced process), and PCBs (Paddle Cards, printed circuit boards).The delivery cycle for small PCBs used inside high-speed optical transceivers has surged from about six weeks to about six months, and is not expected to ease until 2027.

The direct implications of the above statement for the market are that the investment boom in AI infrastructure cannot automatically resolve the structural constraints on the supply side. From a yield rate of less than 30% under stringent laser testing, to TSMC's low unit output in the early stages of advanced packaging, and to PCB supplier switching certification cycles lasting more than six months—multiple bottlenecks overlapping mean that the computing power capacity gap is very likely to continue in a structural manner, and supply chain price increases may become the norm.

Broadcom CEO Hock Tan also confirmed during the March earnings call that Broadcom has secured supplies of key components for 2026 to 2028, covering advanced process wafers, high-bandwidth memory (HBM), and substrates. This forward-looking strategy is a direct reflection of the current supply shortage.

PCB delivery time has increased tenfold.

In 800G/1.6T high-end optical transceiver modules, the PCB is the key interface connecting external cables and internal optoelectronic components. Due to their extremely small size and the need to process extremely high-frequency signals, these small PCBs typically employ mSAP (modified semi-additive process), which has a much higher technical threshold than ordinary PCBs. They are mainly supplied by manufacturers with high-end HDI or IC substrate technologies.

The root cause of PCB becoming a bottleneck lies in the overlap of processes.Its mSAP process overlaps to some extent with the IC substrate process required for AI servers. When the world was scrambling to buy HBM capacity, the capacity of small PCBs was squeezed.At the same time, the 1.6T module has extremely stringent requirements for signal quality, and the PCB must use ultra-low loss materials and precise impedance control, which is not something that ordinary PCB manufacturers can undertake.

More importantly, switching suppliers can take more than six months for certification. This is precisely why hyperscale cloud providers like Google and Meta prefer to sign long-term contracts of three to four years to lock in the capacity of existing suppliers.

Lasers: Yield rate less than 30%, indium phosphide production capacity becomes the core bottleneck.

Laser components have become another major bottleneck in the CPO (co-packaged optics) era. To support bandwidths of 1.6T and even higher, lasers must maintain wavelength stability in the high-temperature environment of data centers, placing stringent requirements on "ultra-high power" and "extremely low noise" continuous wave (CW) lasers.Even if the supplier can produce laser-cut wafers, after rigorous reliability testing, the yield rate that meets CPO's high standards may be less than 30%.

The constraints on production capacity are equally severe. High-power lasers rely on indium phosphide (InP) technology, and there are only a handful of manufacturers worldwide with the capacity for large-scale production of 6-inch InP. If upstream InP epitaxial wafer manufacturers or manufacturers with their own production capacity, such as Coherent and Lumentum, have full order books, then no matter how many packaging plants there are downstream, there will be no laser chips available.

A deeper structural pressure stems from the amplified laser demand inherent in the CPO architecture itself. In traditional optical modules, one module is configured with one laser; however, in the CPO solution, to reduce the thermal impact, the industry has shifted to using the ELSFP (External Laser Source Module) architecture. This has resulted in the demand for laser chips no longer having a linear relationship with the number of switches, but rather increasing exponentially, directly impacting the already strained InP epitaxial capacity.

Wafers and Advanced Packaging: The Real "Super Traffic Jam" is in the Back Lane

Regarding wafer supply, Natarajan Ramachandran stated directly that "TSMC's capacity has reached its limit," and predicted that TSMC's advanced process production lines will reach a bottleneck in 2026, despite TSMC's plan to continue expanding production until 2027.

However, the real "super traffic jam" occurred in the advanced packaging stage.Entering the CPO era, TSMC had to adopt COUPE (Compact Universal Photonic Engine) technology, which uses hybrid bonding to stack optical chips and silicon chips in a three-dimensional manner. This new packaging technology is extremely difficult and has a very long testing cycle, making it difficult to quickly increase the initial unit output (UPH) of the equipment.

The competitive landscape has further exacerbated capacity pressures. By 2026, Broadcom's capacity competitors will no longer be traditional network communication manufacturers, but also Nvidia, Apple, AMD, Qualcomm, and companies like Google, Meta, and OpenAI, which are heavily investing in developing their own ASIC chips. When the most advanced AI computing chips and the highest-end 1.6T network switches simultaneously flood the same production line at TSMC, capacity has essentially entered a "rationing system."

Even if TSMC decides to expand production on a large scale now, the delivery cycle for factory construction, cleanroom completion, introduction of ASML extreme ultraviolet (EUV) lithography equipment and various high-end testing equipment is often twelve to eighteen months.This means that the production capacity for 2026 was actually locked in by major manufacturers between 2024 and 2025 – customers who place additional orders now will have to wait until the new production capacity is released in 2027.

Spillover across the entire supply chain: Second-tier suppliers' capacity expansion lags behind, bottlenecks spread.

Capacity pressures are spilling over into the entire supply chain. Advanced packaging isn't just a matter for packaging plants; the real bottlenecks lie in the following areas:CoWoS requires ABF substrates, underfill for advanced packaging, heat dissipation for the explosive power consumption of AI, KGD testing and burn-in testing, CPO and optical modules, as well as TSV and interposer cutting and drilling, etc.

TSMC Chairman C.C. Wei once stated that "CoWoS capacity is still insufficient"—what he lacks is not capital, but the capacity of supporting suppliers: substrate manufacturers, probe card manufacturers, underfill adhesive suppliers, etc. TSMC can invest heavily in building factories, but it cannot force these small and medium-sized suppliers to double their capacity in the short term. Expanding ABF substrate production often takes two to three years, aging testing takes an extremely long time, and fiber array alignment tolerances are at the sub-micron level, making full automation difficult—every step slows down the overall pace.

As Nvidia continues to advance its GPU architecture hardware iterations, supply chain bottlenecks and price increases are likely to become a structural norm rather than a cyclical disturbance. For investors, the bottlenecks in production capacity are precisely where pricing power is concentrated.